Học liệu
Thiết kế mạch đếm BCD lên xuống trên KIT Altera dùng VHDL
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_BCD_UD is
Port ( clk, clr, UP_Down: in std_logic, ;
segment7_1 : out std_logic_vector( 6 downto 0);
end Counter_BCD_UD;
architecture Behavioral of Counter_BCD_UD is
signal PRESCALER: integer range 0 to 20000000 :=0;
begin
counter_0_59: process (clk)
variable bcd1: std_logic_vector(3 downto 0);
begin
if RISING_EDGE(clk) then
if PRESCALER <20000000 then
PRESCALER <= PRESCALER + 1;
else PRESCALER <= 0;
end if;
if (PRESCALER = 0)then
if (Up_Down='1') then
bcd1:=bcd1+1;
if bcd1 = "1001" then bcd1:="0000";
end if;
elsif (Up_Down='0') then
bcd1:=bcd1-1;
if bcd1 = "0000" then bcd1:="1001";
end if;
end if;
end if;
case bcd1 is
when "0000"=> segment7_1 <="1000000"; -- '0'
when "0001"=> segment7_1 <="1111001"; -- '1'
when "0010"=> segment7_1 <="0100100"; -- '2'
when "0011"=> segment7_1 <="0110000"; -- '3'
when "0100"=> segment7_1 <="0011001"; -- '4'
when "0101"=> segment7_1 <="0010010"; -- '5'
when "0110"=> segment7_1 <="0000010"; -- '6'
when "0111"=> segment7_1 <="1111000"; -- '7'
when "1000"=> segment7_1 <="0000000"; -- '8'
when "1001"=> segment7_1 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7_1 <="1111111";
end case;
END PROCESS;
end Behavioral;
KHOA ĐIỆN - ĐIỆN TỬ ĐẠI HỌC DUY TÂN
Phòng 503 - K7/25 Quang Trung, Tp Đà Nẵng
(0236) 3827111(Ext 503)
dientuvienthong.dtu@gmail.com
